﻿﻿﻿ Daily title - Numbers Group-325

# Daily title - Numbers Group-325

2021-11-30 18:02:36 39 ℃

Every

day

one

question

data structure

1. [Data Structure Research]. Figure G is known as shown below.

computer network

Exam rules: Click on what you think the correct option

2. [Computer Network Postgraduate]. In a network using a CSMA / CD protocol, the transmission medium is a complete cable, the transmission rate is 1Gbps, and the signal propagation speed in the cable is 200 000km / s. If the minimum data frame is reduced by 800 bits, the distance between the farthest two sites is at least required.

C. Reduce 160m

D. Reduce 80M

operating system

Exam rules: Click on what you think the correct option

3. [Operating System Postgraduate] In the system of spooling technology, the user temporarily printed will first be delivered.

A. Disk fixed area

B. Memory fixed area

C. Terminal

D. Printer

Computer composition principle

Exam rules: Click on what you think the correct option

4. [Computer Composition Principle]. A computer main memory is set by byte, and 4 64m * 8-bit DRAM chips are composed of cross-addressing mode, and connected to a memory bus with a width of 32-bit, the main memory Read more 32-bit data at most. If the main memory address of the Double type variable X is 804001ah, the number of stored cycles required to read X is.

A. 1

B. 2

C. 3

D. 4

case

untie

Analyze

data structure

[Analysis]

(2), (3) tomorrow

(1)

computer network

【review】

[Analysis]

Spread delay * 2 = round-trip delay.

Minimum frame transmission delay = propagation delay * 2 = round trip delay.

From the question, send delay and propagation period synchronization reduction: 800Bit transmission delay is: 800b / 1Gbps = 8 * 10 ^ (- 7) s = round-trip delay; propagation time stretching is half of the value: 4 * 10 ^ (- 7) s; so at least the distance is required to increase: 4 * 10 ^ (- 7) S * 200 000 (km / s) = 0.08km = 80m.

operating system

【review】

[Analysis] As described above, the data in this question temporarily unprinted in this question first first sent it from the memory to the output well. When the output device is idle, the data in the output well is sent to the output device on the output buffer. The output well is a storage area opened on the disk, so chooses A.

Computer composition principle

【review】

[Analysis] 4 64m * 8-bit DRAM chip uses cross-addressing mode, modified 4. The lower 2-bit representation body number, the main memory address of the Double type variable X is 804001ah, and it is clear that the low 2 bits are 10, and according to 10MOD4 = 2, the chip numbered 2 is stored. X is a double type, so there is 64 bits, 8 bytes. A storage cycle can read one byte for all chips, so it takes 3 cycles.